The disclosure relates to power management on a chip, and in particular, to improving reliability of a buck converter power stage in the disabled state by applying a force voltage to a switching node. Unless otherwise indicated herein, the approaches described in this section are not admitted to be prior art by inclusion in this section.
For System-On-Chip (SOC) devices, transistors manufactured using a same technology node may be tasked with both power management and data handling roles. In this regard, a SOC PMU (Power Management Unit) offers a design challenge at deeply scaled technology nodes (e.g., 28 nm).
For example, from a power management perspective, the PMU may experience a relatively high input voltage VIN (e.g., V≦4.5V) due to the interface with the battery.
However, from a data management perspective, the maximum voltage (Vmax) which the transistors can withstand may be relatively low (e.g., Vmax=2.0−2.5V for an 1.8V I/O device at 28 nm). For a given technology node this low Vmax constraint can be imposed by considerations of transistor reliability: e.g., Time-Dependent Dielectric Breakdown (TDDB); Hot Carrier Injection (HCl); and Negative Bias Temperature Instability (NBTI).
This issue can offer challenges for designing a conventional buck switching converter power stage. Consider, for example, a conventional buck PMU comprising a PFET/NFET pair.
In the disabled (non-switching) state, the voltage VX at the switching node is typically discharged via the load to a value close to GND, exposing the PFET to a IVGDI (gate to drain voltage) equal to the input voltage VIN. When this VIN exceeds a maximum voltage permissible for reliability purposes (Vmax), so does IVGDI of the PFET. Thus when VIN>Vmax, PMOS reliability can be compromised.
This issue may be addressed by using multiple stacked devices in the power stage, and generating the associated rails to drive and/or bias them. The theoretical maximum allowable VIN is n*Vmax for such a n-stacked power stage.
However, during internal testing/qualification procedures VIN may be raised to a value close to or even exceeding the n*Vmax reliability limit, when the PMU device is in the disabled (non-switching) state. A conventional buck power stage would thus experience this raised VIN (higher than encountered during normal operation) when it is in the disabled state.
Accordingly there is a need to ensure transistors of a buck switching converter power stage are not stressed beyond their reliability limits in the disabled state (e.g., during testing/qualification involving a VIN raised above Vmax).